NPS300

Advanced R&D and pilot line-oriented, the NPS300 is a high accuracy, high force Stepper designed for nano-imprinting.
Optimized for replication of nanostructures at ± 0.5 μm accuracy, the NPS300 is the first-ever tool to combine aligned Hot Embossing Lithography and UV-NIL on the same platform.
The NPS300 can print sub-20 nm geometries with an overlay accuracy of 250 nm.
Its flexible architecture offers excellent process reproducibility and a unique ability to pattern large areas in a sequential Step & Repeat mode on wafers up to 300 mm.
The NPS300 also enables low-cost manufacturing of large stamps with repeated patterns.

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  • Key benefits

    • ± 0.5 μm accuracy
    • Step & Repeat mode on wafers up to 300 mm
    • Automatic stamp pickup
    • Air-bearing technology and granite structure ensure long-term stability and reliability
    • Control of parallelism guarantees exceptional accuracy, even under high forces
    • Hands-free / fully automated calibration
    • Automatic cycle and operator-independent
    • High yield thanks to its stiff design
    • Process recording for development / log files to track production
  • Process capabilities

    Step & Stamp Imprinting Lithography for Hot Embossing and UV-NIL is an innovative method that was demonstrated at the VTT Technical Research Centre of Finland.

    • Hot Embossing Lithography: involves controlling heat and pressure to transfer the stamp pattern into a thermoplastic embossing material.
    • UV-NIL: uses in-situ imprinting material dispensing and UV curing. This cutting-edge technology is a very promising solution for replacing standard UV-lithography systems whenever sub-20 nm resolution is required.
  • Applications

    • Photonic devices
    • High-precision micro-optical arrays and gratings
    • High-resolution OLED displays
    • Large stamp creation
    • Other emerging techniques
  • NIL technology

    Low-cost nanostructure production solutions are in development today, and may be the driving force behind tomorrow’s semiconductor, MOEMS, and optoelectronics technology. In particular, Nanoimprint lithography (NIL) and its variations are being developed as a cost-effective alternative to high-resolution e-beam lithography for printing sub-20 nm geometries.

    Imprinting in a thermo-mechanical or UV curing process is based on the principle of mechanically pressing thin polymer film with a stamp containing the nanopattern. The patterned polymer can act as a final device, e.g., lenses for imaging sensors, microfluidic chips, or biomedical arrays. It can also be used as a high-resolution mask for subsequent process steps.

    Imprinting is a straightforward lithography technology with three basic process steps:

    • Align the stamp with the substrate, which is pre-coated with the imprinting material
    • Press the stamp into the imprinting material to transfer the pattern written on the stamp’s surface

    We identify three imprinting or embossing techniques: Hot Embossing Lithography (HEL) using thermal plastic material, UV-NIL using a liquid resist that is cured with UV light after molding, and Soft Lithography, which uses a stamping method to transfer onto a substrate ink previously applied to a soft stamp.

Technicals papers associated

  • Optimizing indium bump deoxidation through 3D surface profilometry

    MiNaPAD 2026

    G. Chaumy

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  • High Precision Die-to-Wafer Hybrid Bonding: Key Factors for Success

    26-28 June 2023

    P.Metzger

    3D & Systems Summit, Dresden, Germany

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  • Die to wafer hybrid bonding equipment: throughput versus precision

    MiNaPAD 2022

    SET, CEA Leti

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  • Towards 5μm Interconnection Pitch with Die-to-Wafer Direct Hybrid Bonding

    ECTC 2021

    CEA Leti, SET

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  • Die-to-Wafer Direct Bonding for Production Environment with a New Flip-Chip Bonder

    MiNaPAD 2019

    P. Metzger, N. Raynaud

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  • Opto-electronics flip-chip bonding automation and in-situ quality monitoring

    EMPC 2019

    A. Griffart

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  • Die-to-Wafer Direct Hybrid Bonding demonstration with High Alignment Accuracy and Electrical Yields

    3DIC 2019

    CEA Leti, SET

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  • New Flip-Chip Bonder dedicated to Direct Bonding for Production Environment

    ESTC 2018

    SET, CEA Leti

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  • Toward a flip-chip bonder dedicated to direct bonding for production environment

    IWLPC 2017

    IWLPC 2017

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  • Flip-chip bonding: how to meet the high accuracy requirements ?

    EMPC 2017

    C. Avrillier

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  • Toward a Flip-Chip Bonder dedicated to Direct Bonding for Production Environment

    IWLPC 2017

    SET, Saint-Jeoire, France

    3D vertical integration of components is now an industrial reality. Considerations and results on direct bonding for HVM precise assembly are presented.

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  • Quantum Computing

    November 30th, 2017

    Qubit compatible superconducting interconnects

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  • Considerations on the design of high precision Flip-Chip Bonder for mass production

    European 3D Summit 2016

    N. Raynaud

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  • Results of the 2015 testbeam of 180 nm AMS High-Voltage CMOS sensor prototype

    June 30, 2016

    DPNC, University of Geneva, Switzerland

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  • Evaluation of Sn-based Microbumping Technology for Hybrid IR Detectors, 10µm Pitch to 5µm Pitch

    ECTC 2015

    IMEC Leuven, Belgium SOFRADIR Veurey-Voroize, France

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  • Flip-Chip Assembly for Focal Plane Array

    ORION – Moscow International Conference Photoelectronics and Night Vision Devices 2014

    J.-S. Mottet

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  • Development done on Device Bonder to Address 3D Requirements in a Production Environment

    IWLPC 2014

    P. Metzger

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  • Flip-chip assembly for focal plane array

    IST:GST Mumbai 2017

    P. Metzger

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  • Development done on Device Bonder to address 3D requirements in a Production Environment

    IWLPC 2014

    SET, Saint-Jeoire, France

    Key to the success of 3D integration will be the ability to accurately align and bond devices with aggressive feature sizes.

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  • High Density Interconnect Bonding of Heterogeneous Materials Using Non-Collapsible Microbumps at 10 μm Pitch

    June 2014

    RTI International

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  • Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications

    June 2014

    RTI International

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  • Die Attach Bonding using High-frequency Ultrasonic Energy for High-temperature application

    June 2014

    IME – Journal of Electronics materials (abstract)

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  • Microbumping Technology for Hybrid IR detectors, 10µm pitch and beyond

    EPTC 2014

    IMEC Leuven, Belgium SOFRADIR Veurey-Voroize, France

    Singapore

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  • Interconnect and bonding techniques for pixelated X-ray and gamma-ray detectors

    7-12 September, 2014

    UNIVERSITY OF SURREY, Guilford, Surrey, U.K

    10th International Conference on Position Sensitive Detectors

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  • Aluminum to aluminum Bonding at Room Temperature

    ECTC 2013

    CEA – LETI, MINATEC Campus

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  • Micro-tube insertion into aluminum pads: Simulation and experimental validations

    IMAPS 2013

    CEA – LETI, MINATEC Campus

    9th International Conference and Exhibition on Device Packaging

    This material is posted here with permission of IMAPS.

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  • Chip to wafer copper direct bonding electrical characterization and thermal cycling

    December 2013

    CEA – LETI, MINATEC Campus

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  • Die-to-Die and Die-to-Wafer Bonding solution for High Density, Fine Pitch Micro-Bumped Die

    IMAPS Device Packaging Conference 2012

    G. Lecarpentier

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  • Chip to wafer direct bonding technologies for high density 3D integration

    ECTC 2012

    CEA – LETI, MINATEC, STMicroelectronics, SET

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  • NaPANIL “Library of Processes”

    March 2012

    NaPANIL

    Second edition with results of the NaPANIL-project

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  • Chip-to-Wafer Technologies for High Density 3D Integration

    MiNaPAD 2011

    CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics

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  • Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

    IWLPC 2011

    K. Cooper from SET North America

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  • 3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

    IMAPS Device Packaging Conference 2011

    G. Lecarpentier

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  • Low-Profile 3D Silicon-on-Silicon Multi-chip Assembly

    ECTC 2011

    IBM T.J. Watson Research Center

    This material is posted here with permission of IEEE.

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  • A 10 μm Pitch Interconnection Technology using Micro Tube Insertion into Al-Cu for 3D Applications

    ECTC 2011

    CEA – LETI, MINATEC, LEM3 –CNRS/UPV-M

    This material is posted here with permission of IEEE.

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  • Flip-chip die bonding: an enabling technology for 3D integration

    IWLPC 2010

    K. Cooper from SET North America

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  • Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

    IMAPS Device Packaging Conference 2010

    G. Lecarpentier

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  • Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration

    IMAPS 2010

    RTI International

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  • Embedded active device packaging technology for real DDR2 memory chips

    IWLPC 2010

    Industrial Technology Research Institute (ITRI)

    Originally published in the IWLPC Proceedings

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  • SET Technical Bulletin N°3

    February 2010

    CEA-Leti, IMEC, ITRI, IME-A*Star, RTI, etc…

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  • Fabrication and performance of InAs/GaSb-based superlattice LWIR detectors

    SPIE Defense, Sensing & Security 2010

    HRL Laboratories

    Copyright 2010 SPIE

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  • Ultrathin 3D ACA FlipChip-In-Flex Technology

    ECTC 2010

    Berlin Technical University, NB Technologies and Fraunhofer IZM

    This material is posted here with permission of IEEE.

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  • Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process

    ECTC 2010

    Institute of Microelectronics – A*STAR

    This material is posted here with permission of IEEE.

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  • Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration

    ECTC 2010

    IMEC and the Katholieke Universiteit Leuven

    This material is posted here with permission of IEEE.

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  • RF MEMS and flip-chip for space flight demonstrator

    June 2009

    Thales Alenia Space

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  • Electrical characterization of high count, 10 µm pitch, room-temperature vertical interconnections

    Device Packaging 2009

    CEA-LETI

    This material is posted here with permission of Imaps.

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  • UV nanoimprinting lithography using nanostructured quartz molds with antisticking functionalization

    February 2008

    CNR-IMM

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  • UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

    November 2008

    IISB

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  • New Reflow Soldering and Tip in Buried Box (TB2) Techniques For Ultrafine Pitch Megapixels Imaging Array

    ECTC 2008

    CEA-LETI

    This material is posted here with permission of IEEE.

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